NAND flash memories have become widespread as large-capacity memory devices. Cost reduction per bit and capacity increase has recently been achieved by microfabricating memory elements, with further microfabrication expected in future. However, to further reduce the size of a flash memory, many issues must be tackled, such as further development of lithographic techniques, enhancing the short-channel effect, and suppressing interference between elements or variation in the elements. Consequently, it is likely to become difficult to continuously increase storage density merely by the use of simple in-plane microfabrication techniques.
To increase the degree of integration of memory cells, recent research and development has focused on changing the structure of the memory cells from the conventional two-dimensional (planar) structure to a three-dimensional (solid) one, and to this end various types of three-dimensional nonvolatile semiconductor memory devices have been proposed. In a vertical-channel stacked memory as one such three-dimensional device, wherein, for example, a string of memory cells is arranged vertically on the surface of a substrate, insulating layers and electrode layers acting as word lines are alternately stacked on the substrate and then through-holes formed in the resulting structure, thereby forming alternating charge accumulation layers and channel layers (of, for example, silicon) on the inner surface of each through-hole.
In the above-described vertical-channel stacked memory, however, the resistance between memory cells formed on a channel layer may increase and, as a result, reading and writing of the memory cells will become slower. To counter this, a technique of doping a channel layer between memory cells to thereby form an impurity diffusion layer of reduced resistance has been proposed. This technique is, however, problematic in that the impurity diffusion layer may expand undesirably as a result of heat treatment performed after its formation. Such expansion of the impurity diffusion layer impairs the enhanced performance and integration of the vertical-channel stacked memory.